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idgv1g-05a1f1c-[40x/45x/50x] 1gbit x32/x16 gddr5 sgram eu rohs compliant internet data sheet rev. 1.01 october 2008
internet data sheet idgv1g-05a1f1c 1gbit gddr5 graphics ram qag_techdoc_a4, 4.22, 2008-07-22 2 05272008-qt8c-2tyt we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com idgv1g-05a1f1c-[40x/45x/50x] revision history:2008-10, rev. 1.01 page subjects (major chang es since last revision) all typos corrected previous revision: rev. 1.00, 2008-09 5 figure1 - maximum data rate for rdq s mode increased to 3.0 gbps; pl l-off mode restricted to 4.0 gbps previous revision: rev. 0.60, 2008-06 all 36x speed bin removed previous revision: rev. 0.50, 2008-05 all adapted internet version
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 3 05272008-qt8c-2tyt 1overview 1.1 features ? monolithic 1gbit gddr5 sgram (2mbit x 32 i/o x 16 banks and 4mbit x 16 i/o x 16 banks) ? x32/x16 mode configuration set at power-up with edc pin ? quarter data-rate differential clock inputs ck/ck for address and commands ? two half data-rate differential clock inputs wck/wck , each associated with two data bytes (dq, dbi , edc) ? single ended interface for data, address and command ? double data rate (ddr) data (wck) ? single data rate (sdr) command (ck) ? double data rate (ddr) addressing (ck) ? write data mask function (single/double byte mask) via address bus ? 16 internal banks ? 4 bank groups for t ccd = 3 t ck ? 8n prefetch architecture: 256 bit per array read or write access ? burst length: 8 only ? data bus inversion (dbi) and address bus inversion (abi) ? input/output pll on/off mode ? address training: address input monitoring via dq pins ? wck2ck clock training: phase information via edc pins ? data read and write training via read fifo (fifo depth = 6) ? read fifo pattern preload by ldff command ? direct write data load to read fifo by wrtr command ? consecutive read of read fifo by rdtr command ? programmable edc hold pattern for cdr ? data preamble for read ? read/write data transmission integrity secured by cyclic redundancy check (crc?8) ? auto precharge option for each burst access ? programmable cas latency: 6 to 20 t ck ? programmable write latency: 3 to 7 t ck ? programmable crc read latency: 0 to 2 t ck ? programmable crc write latency: 8 to 11 t ck ? digital t ras lockout ? rdqs mode on edc pin ? data output mode for vendor id, density and fifo depth ? low power modes ? on-chip temperature sensor with read-out ? auto refresh and self refresh modes ? 32ms data retention (8k cycles) ? automatic temperature sensor controlled self refresh rate ? on-die termination (odt): nom. values of 60 or 120 ? pseudo open drain (pod?15) compatible outputs (40 pulldown, 60 pullup) ? odt and output driver strength auto-calibration with external resistor zq pin (120 ) ? programmable termination and driver strength offsets ? selectable external or internal vref for data inputs; programmable offsets for internal vref ? separate external vref for address / command inputs ? boundary scan function with sen pin ? mirror function with mf pin ? v dd 1.5v +/- 0.045 v ? v ddq 1.5v +/- 0.045 v ?pg-tfbga 170 ? rohs compliant product 1) 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers.
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 4 05272008-qt8c-2tyt table 1 ordering information 1.2 description the qimonda gddr5 sgram is a high speed dynamic random- access memory designed for applications requiring high bandwidth. it contains 1,073,741,824 bits and is internally configured as a 16-bank dram. the gddr5 sgram uses a 8n prefetch architecture and ddr interface to achi eve high-speed operation. it can be configured to operate in x32 mode or x16 (clamshe ll) mode. the mode is detect ed during device initializat ion. the gddr5 interface transfers two 32 bit wide data words per wck clock cycle to/f rom the i/o pins. corresponding to the 8n prefetch a single write or read access consists of a 256 bit wide, two ck clock cycle dat a transfer at the internal memo ry core and eight corresponding 32 bit wide one-half wck clock cycle data transfers at the i/o pins. the gddr5 sgram operates from a differential clock ck and ck . commands are registered at every rising edge of ck. addresses are registered at every rising edge of ck and every rising edge of ck . gddr5 replaces the pulsed strobes (wdqs & rdqs) used in previous drams such as gddr4 with a free running differential forwarded clock (wck/wck ) with both input and output data registered and dr iven respectively at bo th edges of the forwarded wck. read and write accesses to the gddr5 sgram are burst oriented ; accesses start at a selected location and continue for a total of eight data words. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command and the next rising ck edge are used to select the bank and the row to be accessed. the address bi ts registered coincident with the read or write command and the next rising ck edge are used to select the bank and the column location for the burst access. part number 1) 1) i: qimonda identifier, d: dram, gv: gddr5, 1g: 1gbit, 0: 1 x cs , 5: x32, a1: 1st node, f1: fbga, c: commercial 0 - 85/95c organization max. data rate (gbps/pin) package idgv1g-05a1f1c ? 40x idgv1g-05a1f1c ? 45x idgv1g-05a1f1c ? 50x 32 / x16 4.0 4.5 5.0 pg-tfbga 170
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 5 05272008-qt8c-2tyt 1.3 operating frequency ranges figure 1 provides an overview of the operating frequency range s for pll-on and pll-off operation in normal and rdqs modes. see for a complete list of ac timi ng parameters, for pll-on and pll-off oper ation. pll-off mode is supported for all frequencies. it requires the same interface trainings to be performed. figure 1 operating modes and frequency ranges 037* 1rupdo 0rgh 5'46 0rgh i &. >0+]@ 'dwd5dwh>*esvslq@ 3//2)) 3//2)) 3//21
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 6 05272008-qt8c-2tyt 2 configuration 2.1 signal description table 2 signal description signal type detailed function ck, ck input clock: ck and ck are differential clock inputs. command inputs are latched on the rising edge of ck. address inputs are latched on the rising edge of ck and the rising edge of ck . all latencies are referenced to ck. ck and ck are externally terminated. wck01, wck01 , wck23, wck23 input data clocks: wck and wck are differential clocks used for write data capture and read data output. wck01/wck01 is associated wi th dq0-dq15, dbi0 , dbi1 , edc0 and edc1. wck23/wck23 is associated with dq16-dq31, dbi2 , dbi3 , edc2 and edc3. wck clocks operate at nominally twice the ck clock frequency. cke input clock enable: cke low activates and cke high deactivates internal clock, device input buffers and output drivers. taking cke high provides precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down entry and exit and for self refres h entry and exit. cke must be maintained low throughout read and write accesses. input buffers excluding ck, ck , cke , wck01, wck01 , wck23, wck23 are disabled during power-down. input buffers excluding cke are disabled during self refresh. the value of cke latched at power-up with reset going high determines the termination value of the address and command inputs. cs input chip select: cs low enables, and cs high disables the command decoder. all commands are masked when cs is registered high, but internal command execution continues. cs provides for individual device selection on memory channels with multiple memory devices. cs is considered part of the command code. ras , cas , we input command inputs: ras , cas , and we (along with cs ) define the command to be entered. ba0 - ba3 input bank address inputs: ba0-ba3 select to which internal bank an active, read, write or precharge command is being applied. ba0-ba3 also determine which mode register is accessed with a mode register set command. ba0-ba3 are sampled with the rising edge of ck. a0 - a11 input address inputs: a0-a11 provide the row address for active commands. a0-a5(a6) provide the column address and a8 defines the auto precha rge function for read and write commands, to select one location out of the memory array in th e respective bank. the address inputs also provide the op-code during a mode register set command, and the data bits during ldff commands. a8-a11 are sampled with the rising edge of ck and a0-a7 are sampled with the rising edge of ck . dq0 - dq31 i/o data input/output: 32 bit data bus dbi0 - dbi3 i/o data bus inversion: dbi0 is associated with dq0-dq7, dbi1 with dq8-dq15, dbi2 with dq16- dq23, and dbi3 with dq24-dq31.
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 7 05272008-qt8c-2tyt 2.2 ballout and mirror function mode the gddr5 sgram provides a mirror function (mf) pin to cha nge the physical location of command, address, data and wck pins and assist in routing devices back to back. the pi ns affected by this mirror function mode are listed in table 3 . figure 2 and figure 3 show the ballouts for non-mirrored (mf=0) and mirrored (mf=1) modes. table 3 ball assignment with mirror function functions within the gddr5 sgram that refer to external si gnals are transparent with respect to mirror function mode, meaning that the signal names shown in the respective functional description apply both to mirrored (mf=1) and non-mirrored (mf=0) modes. the referenced package pin is determined by the mirror function mode the devices is configured to. edc0 - edc3 output error detection code: the calculated crc data is transmitted on these pins. used also for x16 mode detection, edc hold pattern and rdqs function . edc0 is associated with dq0-dq7, edc1 with dq8-dq15, edc2 with dq16-dq23, and edc3 with dq24-dq31. abi input address bus inversion zq - impedance reference: external reference pin for auto-calibration reset input reset: reset is a v ddq cmos input. reset low asynchronously initia tes a full chip reset. with reset low all odts are disabled. mf input mirror function: mf is a v ddq cmos input. must be tied to power or ground. sen input scan enable : sen is a v ddq cmos input. must be tied to ground when not in use. v refc supply reference voltage for command and address inputs. v refd supply reference voltage for dq and dbi inputs. v dd , v ss supply power and ground for the internal logic. v ddq , v ssq supply isolated power and ground fo r the input and output buffers. nc - not connected. ball signal ball signal ball si gnal ball signal ball signal mf=0 mf=1 mf=0 mf=1 mf=0 mf=1 mf=0 mf=1 mf=0 mf=1 a2 dq1 dq25 g3 ras cas t4 dq26 dq2 h11 ba0 a2 ba2 a4 e13 dq13 dq21 b2 dq3 dq27 l3 cas ras u4 dq24 dq0 k11 ba2 a4 ba0 a2 f13 dq15 dq23 c2 edc0 edc3 a4 dq0 dq24 d5 wck01 wck23 m11 dq22 dq14 m13 dq23 dq15 d2 dbi0 dbi3 b4 dq2 dq26 h5 a9 a1 a11 a6 n11 dq20 dq12 n13 dq21 dq13 e2 dq5 dq29 d4 wck01 wck23 k5 a11 a6 a9 a1 t11 dq18 dq10 p13 dbi2 dbi1 f2 dq7 dq31 e4 dq4 dq28 p5 wck23 wck01 u11 dq16 dq8 r13 edc2 edc1 m2 dq31 dq7 f4 dq6 dq30 h10 ba3 a3 ba1 a5 g12 cs we t13 dq19 dq11 n2 dq29 dq5 h4 a10 a0 a8 a7 k10 ba1 a5 ba3 a3 l12 we cs u13 dq17 dq9 p2 dbi3 dbi0 k4 a8 a7 a10 a0 a11 dq8 dq16 a13 dq9 dq17 r2 edc3 edc0 m4 dq30 dq6 b11 dq10 dq18 b13 dq11 dq19 t2 dq27 dq3 n4 dq28 dq4 e11 dq12 dq20 c13 edc1 edc2 u2 dq25 dq1 p4 wck23 wck01 f11 dq14 dq22 d13 dbi1 dbi2 signal type detailed function
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 8 05272008-qt8c-2tyt figure 2 ballout, mf = 0 (top view) 033* $ slqlv2))zkhqfrqiljxuhgwr[prgh 9 ''4 9 664 9 ''4 9 664 9 ''4 9 664 0) 9 ''4 9 664 9 ''4 9 664 9 '' 9 '' 9 ''4 9 664 9 66 9 66 ('& '4 '4 '4 '4 9 664 9 664 9 ''4 9 ''4 '4 '4 '4 ('& '4 9 ''4 9 664 9 664 9 ''4 9 ''4 9 664 9 ''4 9 ''4 9 ''4 9 664 9 664 9 ''4 9 ''4 9 664 9 '' :&. 9 664 9 664 $ $ $ $ 9 '' '4 '4 '4 '4 :&. '4 '4 '4 '4 1& $ $ 9 ''4 9 66 9 66 $ $ 9 '' 9 664 9 '' 9 66 9 66 1& 9 ''4 9 664 1& %$ $ '4 '4 %$ $ 9 '' '4 '4 9 '' 9 664 9 664 9 '' 9 '' '4 '4 '4 '4 &. 9 664 9 ''4 9 664 9 ''4 9 664 9 ''4 9 ''4 9 664 9 664 9 ''4 9 ''4 9 664 9 ''4 9 ''4 9 664 9 ''4 9 66 9 ''4 9 664 9 ''4 9 664 9 66 9 '' 9 '' 9 664 9 ''4 9 ''4 9 664 9 664 9 ''4 95()& 9 664 9 ''4 '4 '4 '4 ('& '4 =4 9 664 9 ''4 ('& '4 '4 '4 '4 95()' 95()' %$ $ 6(1 9 66 9 66 9 ''4 9 664 %$ $ 9 66 9 '' 9 664 9 ''4 9 '' 9 66 9 66 9 66 % & ' ( ) * + - . / 0 1 3 5 7 8 '%, :&. 5$6 5(6(7 &.( $%, &$6 '%, :&. '%, &. :( &6 '%,
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 9 05272008-qt8c-2tyt figure 3 ballout, mf = 1 (top view) 033* $ slqlv2))zkhqfrqiljxuhgwr[prgh % & ' ( ) * + - . / 0 1 3 5 7 8 %$ $ '4 '4 %$ $ 9 '' '4 '4 9 '' 9 664 9 664 9 '' 9 '' '4 '4 '4 '4 &. 9 664 9 ''4 9 664 9 ''4 9 664 9 ''4 9 ''4 9 664 9 664 9 ''4 9 ''4 9 664 9 ''4 9 ''4 9 664 9 ''4 9 66 9 ''4 9 664 9 ''4 9 664 9 66 9 '' 9 '' 9 664 9 ''4 9 ''4 9 664 9 664 9 ''4 95()& 9 664 9 ''4 '4 '4 '4 ('& '4 =4 9 664 9 ''4 ('& '4 '4 '4 '4 95()' 95()' %$ $ 6(1 9 66 9 66 9 ''4 9 664 %$ $ 9 66 9 '' 9 664 9 ''4 9 '' 9 66 9 66 9 66 '%, &. :( &6 '%, 9 ''4 9 664 9 ''4 9 664 9 ''4 9 664 0) 9 ''4 9 664 9 ''4 9 664 9 '' 9 '' 9 ''4 9 664 9 66 9 66 ('& '4 '4 '4 '4 9 664 9 664 9 ''4 9 ''4 '4 '4 '4 ('& '4 9 ''4 9 664 9 664 9 ''4 9 ''4 9 664 9 ''4 9 ''4 9 ''4 9 664 9 664 9 ''4 9 ''4 9 664 9 '' :&. 9 664 9 664 $ $ $ $ 9 '' '4 '4 '4 '4 :&. '4 '4 '4 '4 1& $ $ 9 ''4 9 66 9 66 $ $ 9 '' 9 664 9 '' 9 66 9 66 1& 9 ''4 9 664 1& '%, :&. 5$6 5(6(7 &.( $%, &$6 '%, :&.
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 10 05272008-qt8c-2tyt 2.3 addressing the gddr5 sgram uses a ddr address scheme to reduce pins required on the gddr5 sgram as shown in table 4 . the address should be provided to the gddr5 sgram in two parts; t he first half is latched on the rising edge of ck along with the command pins such as ras , cas and we ; the second half is latched on the rising edge of ck . the use of ddr addressing allows all address values to be latc hed in at the same rate as the sdr commands. all addresses related to command access have been positioned for latc hing on the initial rising edge for faster decoding. table 4 address pairs two addressing schemes are supported for x32 mode and x16 mode, which differ only in the number of valid column addresses, as shown in table 5 . table 5 addressing scheme clock edge address inputs rising ck a8 a11 ba1 ba2 ba3 ba0 a9 a10 rising ck a7 a6 a5 a4 a3 a2 a1 a0 32mx32 64mx16 row address a0-a11 a0-a11 column addresses a0-a5 a0-a6 number of banks 16 16 bank address ba0-ba3 ba0-ba3 autoprecharge a8 a8 refresh 8k/32 ms 8k/32 ms refresh period 3.9 s3.9 s page size 2 kb 2 kb bank groups 44
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 11 05272008-qt8c-2tyt 2.4 commands table 6 command truth table 1) h = logic h level; l = logic l level; x = don?t care. signal may be h or l, but not floating 2) addresses shown are logical addresses; physical addresses are inverted when address bus inversion (abi) is activated and abi =l 3) ba0-ba3 provide the mode register address (mra), a0-a11 the opcode to be loaded 4) ba0-ba3 provide the bank address (ba), a0-a11 provide the row address (ra) 5) ba0-ba3 provide the bank address, a0-a5 (a6) provide the column address (ca); no sub-word addressing within a burst of 8 6) this command is refresh when cke(n) = l, and self refresh entry when cke(n) is h 7) ba0-ba3 and ca are used to select burst location (bst) and data respectively 8) deselect and no operation are functionally interchangeable 9) in address training mode read is decoded from the command pins only with ras = h, cas = l, we = h operation code cke n-1 cke n cs ras cas we ba3- ba0 a11 a10 a8 a6-a7, a9 a0-a5 (a6) note device deselect desel l l h x x x x x x x x x 1)2)8) no operation nop l l l h h h x x x x x x 1)2)8) mode register set mrs l l l l l l mra opcode 1)2)3) bank activate act l l l l h h ba row address 1)2)4) read rd l l l h l h ba l l l x ca 1)2)5)9) read with autoprecharge rda l l l h l h ba l l h x ca 1)2)5) load fifo ldff l l l h l h bst h l l data 1)2)7) read training rdtr l l l h l h x h h l x x 1)2) write wr l l lh l lballlx ca 1)2)5) write with autoprecharge wra l l l h l l ba l l h x ca 1)2)5) write with single byte mask wsm l l l h l l ba l h l x ca 1)2)5) write with aut oprecharge, single byte mask wsmalllhl lbalhhx ca 1)2)5) write with double byte mask wdm l l l h l l ba h l l x ca 1)2)5) write with aut oprecharge, double byte mask wdmal l lh l lbahlhx ca 1)2)5) write training wrtr l l l h l l x h h l x x 1)2) precharge pre l l l l h l ba x x l x x 1)2) precharge all preall l l l l h l x x x h x x 1)2) refresh ref lllll hx xxxx x 1)6) power down mode entry pde l h h x x x x x x x x x 1) lh h h power down mode exit pdx h l h x x x x x x x x x 1) lh h h self refresh entry sre l h l l l h x x x x x x 1)6) self refresh exit srx h l h x x x x x x x x x 1) lh h h
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 12 05272008-qt8c-2tyt 3 mode registers the mode registers define the specific mode of operation. mr0 to mr7 and mr15 are defined as shown in the overview in figure 4 . mr8 to mr14 are not used. all mode registers are programmed via the mode register set (mrs) command and will retain the stored information until they are reprogrammed or a subsequent reset. mode regist ers must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent operation. violating either of these requirements will result in unspecified operation. all mode registers are initialized upon reset with all 0?s (excepti on: mr4, bits a0-a3: ?1111?). however, the user shall progra m all mode registers to the desired va lues e.g upon device initialization. reserved states should not be used, as unknown operation or incompatibility wi th future versions ma y result. rfu bits are reserved for future use and must be programmed to 0. figure 4 mode registers overview 03%* 05 05 ('& ,19 05 05 05 05 05 :ulwh/dwhqf\ :/puv :ulwh5hfryhu\:5 &$6/dwhqf\&/puv 95()'2iivhw %\whvlqurzv08 95()'2iivhw %\whvlqurzv$) 5$6 3//%dqgzlgwk ('&+rog3dwwhuq &5&5hdg /dwhqf\ &5&:ulwh /dwhqf\ ,qir 6hoi5hiuhvk :&. 7huplqdwlrq %dqn*urxsv 3xoogrzq 'ulyhu2iivhw 3xooxs 'ulyhu2iivhw 'dwd:&. 7huplqdwlrq2iivhw $gguhvv&rppdqg 7huplqdwlrq2iivhw 'ulyh 6wuhqjwk 'dwd 7huplqdwlrq $ggu&pg 7huplqdwlrq %$ %$ %$ %$ $ 3// 5hvhw $ :5 &5& $%, $ 5' &5& :'%, $ 5'%, 7hvw 0rgh $ 3// $ &do 8sg $ 2$13 -ode $ :&. &. $ :&. ,19 $ /3 $ $ /3 /3 5)8 :&. ,19 :&. 3,1 05 5)8 5)8 95()' +doi 95()' '4 3uh$ 5)8 /rz) 0rgh 05 5)8 $'7 ; ; ; ; ; 05( 0) 05( 0) ; ; ; 5)8
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 13 05272008-qt8c-2tyt 4 electrical characteristics 4.1 absolute maximum ratings table 7 absolute maximum ratings attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage of the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operationa l sections of these specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol ratings unit min. max. device supply voltage v dd -0.5 2.0 v output buffer supply voltage v ddq -0.5 2.0 v input voltage v in -0.5 2.0 v output voltage v out -0.5 2.0 v storage temperature t stg -55 +150 c junction temperature t j ? +125 c short circuit output current i out ?50ma
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 14 05272008-qt8c-2tyt 4.2 operation conditions table 8 dc operating conditions parameter 1) 1) 0c tc 95c. all voltages are measured at the package pins. symbol pod-15 unit notes min. typ. max. device supply voltage v dd 1.455 1.5 1.545 v 2) 2) gddr5 sgrams are designed to tole rate pcb designs with separate v ddq and v dd power regulators. output supply voltage v ddq 1.455 1.5 1.545 v 2) reference voltage for dq/dbi inputs v refd 0.69 * v ddq 0.71 * v ddq v 3)4) 3) ac noise in the system is estimated at 50mv peak-to-peak for the purpose of dram design. 4) source of reference voltage and control of reference voltage for dq and dbi pins is determined by vrefd, half vrefd and vrefd offset mode registers. reference voltage for dq/dbi inputs v refd2 0.49 * v ddq 0.51 * v ddq v 3)4)5) 5) vrefd offsets are not supported with v refd2 . reference voltage for command and address inputs v refc 0.69 * v ddq 0.71 * v ddq v 6) 6) external v refc is to be provided by the controller as there is no alternative supply. input logic high voltage for address/command inputs v iha(dc) v refc + 0.15 ? v input logic low voltage for address/command inputs v ila(dc) ? v refc - 0.15 v input logic high voltage for dq/dbi inputs with v refd v ihd(dc) v refd + 0.1 ? v input logic low voltage for dq/dbi inputs with v refd v ild(dc) ? v refd - 0.1 v input logic high voltage for dq/dbi inputs with v refd2 v ihd2(dc) v refd2 + 0.3 ? v input logic low voltage for dq/dbi inputs with v refd2 v ild2(dc) ? v refd2 - 0.3 v input logic high voltage for reset , sen + mf inputs v ihr v ddq - 0.5 ? v input logic low voltage for reset , sen + mf inputs v ilr ?0.3v input logic high voltage for edc1/2 (x16 mode detect) v ihx v ddq - 0.3 ? v 7) 7) v ihx and v ilx define the input voltage levels for the receiver that detects x32 mode or x16 mode with reset going high.. input logic low voltage for edc1/2 (x16 mode detect) v ilx ?0.3v 7) ck, ck , wck and wck single ended input voltage v inck - 0.3 v ddq + 0.3 v clock input mid-point voltage v mp(dc) v refc - 0.1 v refc + 0.1 v 8)9)10)11) 8) this provides a minimum of 0.95v and a maximum of 1.15v, and is always 70% of v ddq with pod-15. dram timings relative to ck cannot be guaranteed if these limits are exceeded. . 9) for ac operations, all dc clock requirements must be satisfied as well. ck/ck dc input differential voltage v idck(dc) 0.22 ? v 9)11)12) wck/wck dc input differential voltage v idwck(dc) 0.2 ? v 9)13)14) input leakage current (any input 0 v v in v ddq ; all other pins not under test = 0 v) i il -5 +5 a 15) output leakage current (dqs are disabled; 0 v v out v ddq ) i oz -5 +5 a output logic low voltage v ol(dc) ?0.62v external resistor value zq 115 120 125
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 15 05272008-qt8c-2tyt table 9 ac operating conditions 10) the value of v ixck and v ixwck is expected to equal 70% of v ddq for the transmitting device and must track variations of the dc level of the same. 11) the ck and ck input reference level (for timing referenced to ck and ck ) is the point at which ck and ck cross. 12) v idck is the magnitude of the difference between the input level on ck and the input level on ck . 13) the wck and wck input reference level (for timing referenced to wck and wck ) is the point at which wck and wck cross. 14) v idwck is the magnitude of the difference between the input level on wck and the input level on wck . 15) i il and i ol are measured with odt off. parameter 1)2) 1) 0c tc 95c. all voltages are measured at the package pins. 2) for optimum performance it is recommended that si gnal swings are larger than shown in the table. symbol pod-15 unit notes min. typ. max. input logic high voltage for address/command inputs v iha(ac) v refc + 0.2 ? v input logic low voltage for address/command inputs v ila(ac) ? v refc - 0.2 v input logic high voltage for dq/dbi inputs with v refd v ihd(ac) v refd + 0.15 ? v input logic low voltage for dq/dbi inputs with v refd v ild(ac) ? v refd - 0.15 v input logic high voltage for dq/dbi inputs with v refd2 v ihd2(ac) v refd + 0.4 ? v input logic low voltage for dq/dbi inputs with v refd2 v ild2(ac) ? v refd - 0.4 v ck/ck input differential voltage v idck(ac) 0.4 ? v 3)4) 3) the ck and ck input reference level (for timing referenced to ck and ck ) is the point at which ck and ck cross. 4) v idck is the magnitude of the difference between the input level on ck and the input level on ck . wck/wck input differential voltage v idwck(ac) 0.3 ? v 5)6) 5) the wck and wck input reference level (for timing referenced to wck and wck ) is the point at which wck and wck cross.. 6) v idwck is the magnitude of the difference between the input level on wck and the input level on wck . ck/ck input crossing point voltage v ixck(ac) v refc - 0.12 v refc + 0.12 v 3)7) 7) the value of v ixck and v ixwck is expected to equal 70% of v ddq for the transmitting device and must track variations of the dc level of the same. wck/wck input crossing point voltage v ixwck(ac) v refd - 0.1 v refd + 0.1 v 5)7)
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 16 05272008-qt8c-2tyt 5 package 5.1 package outline figure 5 package outline )32b3*7)%*$bb
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 17 05272008-qt8c-2tyt list of illustrations figure 1 operating modes and frequency ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2 ballout, mf = 0 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3 ballout, mf = 1 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4 mode registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 18 05272008-qt8c-2tyt list of tables table 1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3 ball assignment with mirror function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4 address pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5 addressing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6 command truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8 dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9 ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
idgv1g-05a1f1c 1gbit gddr5 graphics ram internet data sheet rev. 1.01, 2008-10 19 05272008-qt8c-2tyt contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 operating frequency ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 ballout and mirror function mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
edition 2008-10 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2008. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein an d/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any ki nd, including without limitation warranties of non-infringement of in tellectual property righ ts of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. under no circumstances may the qimonda product as referred to in this internet data sheet be used in 1. any applications that are intended for military usage (including but not limited to weaponry), or 2. any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices an d systems collectively referred to as "critical systems"), if a) a failure of the qimonda product can reasonable be expected to - directly or indirectly - (i) have a detrimental effect on such critical systems in terms of reliability, effectiveness or safety; or (ii) cause the failure of such critical systems; or b) a failure or malfunction of such critical systems ca n reasonably be expected to - directly or indirectly - (i) endanger the health or the life of the user of such critical systems or any other person; or (ii) otherwise cause material damages (including but not lim ited to death, bodily injury or significant damages to property, whether tangible or intangible). www.qimonda.com internet data sheet

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